Gigg från: PrimeComp AB
Prime Comp is a technology and consulting company with assignments in energy, industry, and infrastructure. Through our combined experience and unique range of technology areas, we offer services to create profitable, innovative, and sustainable solutions. We work with leading global companies in the private sector, but we also target the public sector. Prime Comp is primarily aimed at project managers and technical competencies in mechanical engineering, electrical power, electronics, electrical/automation, and embedded systems. Assignment: We are looking for an experienced FPGA designer, with a passion for backend design, to one of our team working towards the telecom industry. The teams work mainly derives of tasks like: Block or Top Level Floor planning Bus/Pin Planning, Clock Tree Synthesis Placement, Optimization Routing, Static Timing Analysis But there might also be task that requires knowledge in lab environment. The team way of working is agile and high collaboration skills are needed to be able to work with other team members and teams. Key competences: VHDL/Verilog programming experience Experience with Xilinx and/or Altera platform and tools (Quartus or ISE etc.) Experience in Xilinx/Altera backend flow Floor planning Timing analysis Experience in multigigabit transceivers Scripting (TCL, Python, Perl) Worked with tools as: Spyglass Cadence Clearcase
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